AUTOMATION TOOL FOR LAYOUT DESIGN OF VLSI CELLS
The article is devoted to the description the design tools optimized cell layout of integrated circuits. Developed software tools generate textual description of process tolerant layout sketches, which are configured on the user required design rules by layout compaction tool.
Authors: S. E. Mironov, A. K. Frolkin
Direction: Informatics, management and Computer Technology
Keywords: Cell layout, VLSI, element placement, Euler path, tracing, layout optimization, process tolerant layout design
View full article