PROCESS-TOLERANT CAD OF CMOS VLSI HIERARCHICAL MACROBLOCK TOPOLOGY
Article is devoted to the description of the developed system of VLSI macroblocks hierarchical layout design in process-tolerant concept. Describes the graphical editor, base components and their properties and types of implemented macroblocks.
Authors: S. E. Mironov, A. U. Vasilev
Direction: Informatics, management and Computer Technology
Keywords: Hierarchical topology design, topology compaction, process-tolerant design, VLSI macroblock, matching cells
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